1. Field of the Invention
The present invention relates to a clock recovery circuit, a receiver having the clock recovery circuit and a method of recovering a clock signal.
For convenience of description the present invention will be described with reference to a receiver.
2. Description of the Related Art
In receivers used for receiving digital signals, such as pagers and cellular and cordless telephones, received signals are demodulated, decoded and transformed into Non-Return to Zero (NRZ) data of 1 or 2 bits. In order to make the information complete and suitable to be processed, a locally generated synchronisation clock is required. A clock recovery circuit is provided for generating this synchronisation clock.
U.S. Pat. No. 5,418,822 discloses a circuit arrangement for generating a clock signal from a digital signal by evaluating signal edges of the digital signal. A first device generates a pulse at a signal edge oriented in a first direction, and a second device generates a pulse at a signal edge oriented in a second direction which is opposite to the first direction. Each of the devices has one terminal for receiving a digital signal and one output. A voltage-controlled, triggerable oscillator device has at least two trigger inputs, one control input and one output. Each of the trigger inputs is connected to the output of a respective one of the first and second devices, and the output of the oscillator device is an output for the clock signal. An integration device has an input connected to the output of the oscillator device and has an output connected to the control input of the oscillator device. The purpose of this circuit arrangement is to produce a clock signal that is synchronous in both frequency and phase with the clock signal that is fundamental to the data in the digital signal.
A disadvantage of clock recovery circuits which synchronise to the rise and fall edges is that if there are changes in the group delay of the transmitter then a relative shifting occurs between the rise and fall edges of the recovered data leading to jitter and loss of sensitivity in the generated clock signal.
An object of the present invention is to avoid loss of sensitivity in the clock recovery of a FSK signal.
According to one aspect of the present invention there is provided a receiver comprising receiving means for receiving a data signal and providing a base band output, demodulating means coupled to an output of the receiving means for providing a data output, and symbol recovery means coupled to an output of the demodulating means for recovering symbols represented by the data output, characterised in that the symbol recovery means comprises means for determining the occurrence of rising and falling edges in the data output, means for determining the differences between the occurrence of the rising and falling edges and means for utilising the differences for determining a clock reference position.
According to a second aspect of the present invention there is provided a clock recovery circuit comprising means for determining the occurrence of rising and falling edges in a data signal, means for determining the differences between the occurrence of the rising and falling edges and means for utilising the differences for determining a clock reference position.
In one embodiment of the present invention the means for determining a time difference between rising and falling edges in the data output and their nominal reference points produces a time difference signal. Additionally phase locked loop means (PLL) is provided having input means for the rising and falling edges and the time difference signal and means for calculating respective reference positions for the rise and fall edges.
By the phase locked loop means calculating the respective reference positions for the rising and falling edges, the phase locked loop means will not advance or retard for each symbol change because the rising and falling edges are close to their respective calculated reference positions. As a result jitter due to different bit length is greatly reduced without decreasing the bandwidth of the phase locked loop means. The problem of the sensitivity degradation due to a difference in the bit length is solved without changing the bandwidth of the phase locked loop means. Additionally the frequency stability requirements on the phase locked loop reference oscillator are not, stringent which permits the usage of less highly specified, cheaper crystals.
In a second embodiment of the present invention respective rising and falling edge phase locked loop means are provided for noting the occurrence of a respective edge position relative to a predetermined phase and averaging means are provided for determining a clock reference position from a circular, mean of the phases in the respective phase locked loop.
According to a third aspect of the present invention there is provided a method of recovering symbols in a data signal, comprising determining the occurrence of rising and falling edges in the data signal, determining the differences between the occurrence of the rising and falling edges, and utilising the differences for determining a clock reference position.